From the first invention of integrated circuits in 1960, the number of devices on a chip has grown in an explosive increasing rate. The technologies of the semiconductor industry has been researched continuously for almost four decades. The progress of the semiconductor integrated circuits has step into ULSI (ultra large scale integration) level or even higher level. The capacity of a single semiconductor chip increases from several thousand devices to hundreds of million devices, or even billions of devices. The integrated circuits devices like the transistors, the capacitors, and the connections must be greatly narrowed simultaneously.
The increasing packing density of the integrated circuits generates numerous challenges to the semiconductor manufacturing process. Every device needs to be formed within smaller size without damaging the characteristics and the operations. The demands on high packing density, and low heat generation devices with good reliability and long operation life must be maintained without any degradation in their functions. In more and more applications for portable and battery-operated devices like computer and communications systems, the low power consuming design is the main issue. Low power technologies in devices and manufacturing processes are highly required.
All the challenges and demands in fabrication are expected to be solved with the five key aspects of the semiconductor manufacturing, including the photography, the etching, the deposition, the ion implantation, and the thermal processing technologies. The continuous increase in the packing density of the integration circuits must be accompanied with a smaller feature size. In addition to chip area and functional considerations, all the devices with smaller size must be achieved with simplified or reduced manufacturing steps to raise the throughput and reduce the cost of products.
For the design of present stage devices, low threshold devices are expected for performance and power considerations especially in sub-micrometer and smaller size technologies. High threshold devices are also expected in the circuits to operate with reduced leakage current. Thus, integrated circuit chips with dual threshold devices have became one of the vital functional design. Dual threshold CMOS (complementary metal semiconductor oxide) circuits has been reported to provide better retention time in DRAM (dynamic random memory) design applications.
T. Kuroda et al. disclosed the characteristics of different approaches on dual threshold circuits and dynamic threshold circuits, in the work "A 0.9-V, 150-MHz, 10-mW, 4 mm.sup.2, 2-D Discrete Cosine Transform Core Processor with Variable Threshold-Voltage (VT) Scheme" (in IEEE Journal of Solid-State Circuits, Vol. 31, No. 11, 1996). It is introduced that lowering both the supply voltage V.sub.DD and threshold voltage V.sub.th enables high-speed, low-power operation. However, the approach raises the problems of degradation of worst-case speed due to V.sub.th fluctuation in low V.sub.DD and the increase in the standby power dissipation in low V.sub.th.
Several schemes in solving the problems are compared. A self-adjusting threshold voltage (SAT) scheme reduces Vth fluctuation in an active mode by adjusting substrate bias with a feedback control circuit. A standby power reduction (SPR) scheme raises V.sub.th in a standby mode by switching substrate bias between the power supply and an external additional supply higher than V.sub.DD or lower than GND. T. Kuroda et al. also introduced a dual or a multi threshold circuit for fast circuit operation and high V.sub.th for providing and cutting internal supply voltage. A circuit technique for dynamically varying threshold voltage (V.sub.T scheme) is disclosed the their work.
The benefits in improved retention time and reduced critical path delay of DRAM application has been illustrated by S. Thompson et al. (in the article "Dual Threshold Voltages and Substrate Bias: Keys to High Performance, Low Power, 0.1 .mu.m Logic Designs", 1997 Symposium on VLSI Technology Digest of Technical Papers). The advantages of dual threshold devices in the applications of DRAM and static CMOS logic critical paths are disclosed. The reduced pass transistor leakage for improved DRAM retention time and reduced critical path delay through the use of a highly leaky low threshold device in static critical path circuits. It is shown in the work that dual threshold voltage devices and substrate bias are needed in high performance low power 0.1 micrometer logic designs.
In general, one or more additional masks are needed in conventional method for forming dual threshold circuits, in compared with single threshold circuits. Z. Chen et al. disclose a process in the work "0.18 .mu.m Dual V.sub.t MOSFET Process and Energy-Delay Measurement" (in IEDM Tech. Dig., p. 851, 1996). They also disclosed that the challenge to maintain the performance and reduce the power consumption for battery operated applications has let to significant progress on low power technology and low power design. On the technology side, it has become gradually accepted that low threshold devices are vital for performance at low voltages. To overcome the issue of high leakage current associated with the low threshold devices, dual Vt processes are also realized. The objective is to use the low Vt devices for the few critical paths and high Vt devices for the non-critical paths. The process and measurement of dual Vt MOSFET are provided in the article.
For achieving dual threshold CMOS circuits, more efforts and masks are needed in the conventional process. What is highly demanded is a simplified reduced manufacturing process with reduced steps to raise the throughput and reduce the cost of products in fabricating dual threshold CMOS circuits.